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Description: JPEG encoder VHDL code
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Size: 210944 |
Author: liruoyu |
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Description: this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
-this project is based on 8*3 encoder and 3*8 decoder using vhdl.this is the 100 correct code,reference is taken from book digital electrionics written by anand kumar.please use quatrus to access this code.this code can be used for the final year project for engineering.
Here dataflow techniques and behavioural
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Size: 142336 |
Author: jatab |
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Description: 步进电机的转动控制程序,可用于变速,和编码器混合使用-Stepper motor rotation control program can be used for variable speed, and mixed use encoder
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Size: 1024 |
Author: 强强 |
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Description: HDB3编码器与译码
HDB3编码器与译码-HDB3 encoder and decoder
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Size: 266240 |
Author: 一天 |
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Description: jpeg 2000 encoder complete document
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Size: 378880 |
Author: ibbu |
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Description: 8b/10b encoder/decoder vhdl source-8b/10b encoder/decoder vhdl source
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Size: 141312 |
Author: ZES |
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Description: jpeg encoder vhdl source code
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Size: 2244608 |
Author: ZES |
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Description: reed solomon encoder (255,239) verilog source code
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Size: 4096 |
Author: 梅国强 |
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Description: viterbi decoder with convolutional encoder
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Size: 1389568 |
Author: phani |
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Description: DVBC RS编码,标准TS流输入输出接口!-DVBC RS encoder
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Size: 3072 |
Author: sun mingang |
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Description: Energy efficient for turbo encoder decoder
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Size: 536576 |
Author: suresh |
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Description: vhdl code for convolutional encoder
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Size: 2048 |
Author: anjali |
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Description: a VHDL implementation of 255_239 reed solomon encoder.
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Size: 3072 |
Author: saad |
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Description: 适用于10GBase-T的以太网(802.3an协议)LDPC, VERILOG语言编写,可以应用在LATTICEXP2系列芯片上,基于Gallager算法。-LDPC encoder for 10GBase-T Ethernet (802.3an), based on Gallager s A algorithm
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Size: 620544 |
Author: liang |
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Description: verilog code for viterbi encoder and decoder
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Size: 13312 |
Author: kamran |
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Description: VHDL实现的16B/20B编码器。由两个8B/10B编码器组成。级联实现。-VHDL implementation 16B/20B encoder. Composed by two 8B/10B encoder. Cascade realization.
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Size: 78848 |
Author: kvein |
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Description: 编码器和译码器,Verilog实现,有具体实验说明文档。-Encoder and decoder, Verilog realization of a specific experiment documentation.
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Size: 1628160 |
Author: mypudn0001 |
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Description: 用VERILOG实现的,hdb3编码器和解码器,经过前仿真和后仿真成功-Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation
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Size: 435200 |
Author: Along |
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Description: 编码方式为213的Viterbi卷积码编码器和译码器的FPGA的实现,包含整个QuartusII的工程文件,解码方式为寄存器交换法-Encoding for the 213 convolutional code encoder and Viterbi decoder FPGA realization of the project file that contains the entire QuartusII, decoding method for the register exchange
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Size: 2668544 |
Author: jenny |
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Description: ADPCM ENCODER and
DECODER
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Size: 1513472 |
Author: hr |
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